ds2502e64 ieee eui64 node address chip ds2502e64 preliminary 021998 1/2 features ? ieeeapproved factory programmed 64bit node address chip (eui64) with 768 bits userprogram- mable otpeprom communicates with the econ- omy of one signal plus ground ? meets the node identification requirements of ieee standard 13941995 (firewire tm ) ? unique, factory lasered and tested 64bit registration number (8bit family code 89h + 36bit serial number + 12bit uniqueware identifier 5e7h + 8bit crc tes- ter) assures absolute traceability because no two parts are alike ? builtin multidrop controller ensures compatibility with other microlan tm products ? device is an aadd onlyo memory where additional data can be programmed into eprom without disturbing existing data ? reduces control, address, data, power and program- ming signals to a single pin ? directly connects to a single port pin of a microproces- sor and communicates at up to 16.3k bits per second ? presence detector acknowledges when reader first applies voltage ? low cost to92 or tsoc surface mount packages ? reads over a wide voltage range of 2.8v to 6.0v from 40 c to +85 c; programs at 11.5v to 12.0v from 40 c to +50 c 3 2 1 ds2502e64 yywwrr cccccc to92 bottom view gnd tsoc package top view the dot marks pin 1 side view see mech. drawings section data nc nc data gnd nc nc nc yyww = date code rr = die revision code cccccc = country code e64 2502 yyww ordering information ds2502e64 to92 package ds2502pe64 6pin tsoc package global identifier description the ds2502e64 is a variant of the ds2502 1024bit addonly memory. it differs from the standard ds2502 in its custom rom family code 89h, and the unique- ware identifier 5e7 in place of the upper 12 bits of the standard rom serialization field. otherwise, the electri- cal and logical behavior is identical to that of the ds2502. for technical details please refer to the ds2502 data sheet. the first 32 bytes of the ds2502e64's eprom memory contain a globally unique 64bit node address (eui64) and are writeprotected. the data structure follows the conventions of uniqueware devices using default data structure (figure 1). the data record starts with a length byte (0ch) and the 4byte uniqueware project id 00001128h. the next eight bytes contain the eui64 global identifier (node address) which consists of an incrementing 40bit extension identifier and the ieeeassigned 24bit com- pany id value 006035h. a 16bit crc ends the data record. the remaining bytes of the 32byte memory page remain unprogrammed. neither the 40bit exten- sion identifier nor the 24bit company id are related to
ds2502e64 021998 2/2 the 64bit rom registration number, which is distinct from the ieee standard 13941995 node address. the rom registration number is used to provide a unique address to access the ds2502e64 when multi- dropped on a 1wire tm bus. firewire tm is a trademark of apple computer, inc. eui64 node address chip data structure figure 1 (unused) crc16 company id value extension id value project id length msb lsb msb lsb msb lsb msb lsb 17 bytes ffh 2 bytes 3 bytes constant 006035h 5 bytes serialization 4 bytes constant 00001128h 1 byte 0ch high address low address example assume that a manufacturer's company id value is 006035 16 and the 40bit extension identifier is 234567abcd 16 . the eui64 value generated from these two numbers is 006035234567abcd 16, whose byte and bit representations are illustrated in figure 2. this information is stored in the ds2502e64 as 64bit number with the least significant byte at the lower address. including the length byte and the crc, the complete set of data is shown in figure 3. the four bytes at memory addresses 01 to 04 contain the uniqueware project id 00001128 16 . the two bytes at addresses 0dh and 0eh are the 16bit crc over the length byte, project id and eui64 value. the least sig- nificant byte of the crc is stored at address 0d. this crc is generated according to the standardized crc16 polynomial function x 16 + x 15 + x 2 + 1. for more details on generating crc values including examples in both hardware and software, see the abook of ds19xx i button standardso or application note 27. the contents of the memory address range 0fh to 1fh is ffh. these cells cannot be altered since the whole memory page is writeprotected. the memory range from 20h to 7fh, however, is userprogrammable. it can be writeprotected by programming the corre- sponding writeprotect bit in the status memory of the ds2502e64. sample eui64 value figure 2 hex 0000 0000 00 0110 0000 60 0011 0101 35 0010 0011 23 0100 0101 45 0110 0111 67 1010 1011 ab 1100 1101 cd most significant least significant byte byte most significant least significant bit bit binary physical address and data mapping inside the device figure 3 address 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 data xx xx 00 60 35 23 45 67 ab cd 00 00 11 28 0c xx xx = crc16, value depends on actual data
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